--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   22:10:12 06/05/2010
-- Design Name:   
-- Module Name:   C:/Users/Tom/Documents/lcpd-scope/vhdl/project/Average_Filter_TB.vhd
-- Project Name:  LCPD_Scope
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Average_Filter
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY Average_Filter_TB IS
END Average_Filter_TB;
 
ARCHITECTURE behavior OF Average_Filter_TB IS 
    
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Average_Filter
    PORT(
         Data_in : IN  std_logic_vector(11 downto 0);
         Data_out : OUT  std_logic_vector(11 downto 0);
         reset : IN  std_logic;
         divider : IN  std_logic_vector(7 downto 0);
         newdata_in : IN  std_logic;
         newdata_out : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal Data_in : std_logic_vector(11 downto 0) := (others => '0');
   signal reset : std_logic := '0';
   signal divider : std_logic_vector(7 downto 0) := (others => '0');
   signal newdata_in : std_logic := '0';

 	--Outputs
   signal Data_out : std_logic_vector(11 downto 0);
   signal newdata_out : std_logic;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Average_Filter PORT MAP (
          Data_in => Data_in,
          Data_out => Data_out,
          reset => reset,
          divider => divider,
          newdata_in => newdata_in,
          newdata_out => newdata_out
        );
 
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
--constant newdata_in_period := 10 ns;
 
   newdata_in_process :process
   begin
		newdata_in <= '0';
		wait for 5 ns;
		newdata_in <= '1';
		wait for 5 ns;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin	
		divider <= "00000011";
		Data_in <= "111111111111";
		wait for 10ns;
		Data_in <= "111111111111";
		wait for 10ns;
		Data_in <= "111111111111";
		wait for 10ns;
		Data_in <= "000000000000";
				wait for 10ns;
		Data_in <= "111111111111";
		wait for 10ns;
		Data_in <= "000000000000";
				wait for 10ns;
		Data_in <= "111111111111";
		wait for 10ns;
		Data_in <= "000000000000";
      wait for 100ns;

      -- insert stimulus here 

      wait;
   end process;

END;
